It then compares that conversion to the input signal.ģ. While SARs progress through each step by going to the next most significant digit (sixteen to eight to four and so on), the pipelined ADC uses the following process:Ģ. Pipelined ADC: Pipelined ADCs, also called “subranging quantizers,” are similar in concept to SARs, but more refined. As a result, they are very well-suited to high-fidelity audio applications, but they’re typically not usable where more bandwidth is necessary (such as video). Sigma Deltas are very slow compared to other designs but offer the highest resolution of all ADC types. Sigma-Delta ADC: ΣΔ is a relatively recent ADC design. SAR ADCs are considerably slower than flash ADCs, but they offer higher possible resolutions without the component size and cost of flash systems. Continue this process until the resolution maxes out or you achieve the desired resolution. Therefore, we compare the 5V signal to a range of 4-8V, found to be below the midpoint of the range. For example, a 5V input signal is above the midpoint of a 0 – 8V range (midpoint is 4V). These ADCs use a comparator to compare input voltage and the output of an internal digital-to-analog converter, successively judging whether the input is above or below a narrowing range’s midpoint. Successive Approximation (SAR): We can identify these ADCs by their successive approximation registers, which gives them the nickname SAR. On the other hand, semi-flash converters take twice as long as flash converters, though they are still very fast. One flash converter handles the most significant bits while the other handles the least significant bits (reducing the components to 2*2 N/2-1, resulting in 8-bit resolution with 31 comparators). Semi-flash ADC: Semi-flash ADCs work around their size limitation by using two separate flash converters, each with a resolution of half the bits of the semi-flash device. You can find flash ADCs at use in video digitization or fast signals in optical storage. They require 2 N-1 comparators, where N is the number of bits (8-bit resolution, therefore, requires 255 comparators). As a result, they tend to be large and expensive compared to other ADCs. They achieve these speeds by running a bank of comparators that operate in parallel, each for a defined voltage range. We can evaluate ADC performance using several factors, the most important of which are:ĪDC Signal-to-noise ratio (SNR): The SNR reflects the average number of non-noise bits in any particular sample (effective number of bits or ENOB).ĪDC Bandwidth: We can determine bandwidth by evaluating the sampling rate – the number of times per second the analog source is sampled to generate discrete values.įlash and Half (Direct Type ADC): Flash ADCs, also called “direct ADCs” are very fast-capable of sampling rates in the gigahertz range. Each ADC architecture has its own distinct strengths and weaknesses. As a result, the analog-to-digital process will always involve a certain amount of noise or error, however small.ĭifferent types of converters achieve this quantization in different ways, depending on their architecture. An ADC performs this conversion by some form of quantization – mapping the continuous set of values to a smaller (countable) set of values, often by rounding.
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